Table of Contents
VLSI Design
Volume 7, Issue 4, Pages 347-352
http://dx.doi.org/10.1155/1998/10193

Testability-Driven Layout of Combinational Circuits

Department of Electrical Engineering, Indian Institute of Technology, New Delhi 110016, India

Received 27 June 1994; Accepted 1 August 1995

Copyright © 1998 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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