VLSI Design

VLSI Design / 1998 / Article
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High Performance Design Automation of VLSI Interconnects

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Volume 7 |Article ID 038483 | https://doi.org/10.1155/1998/38483

Michael J. Alexander, James P. Cohoon, Joseph L. Ganley, Gabriel Robins, "Placement and Routing for Performance-Oriented FPGA Layout", VLSI Design, vol. 7, Article ID 038483, 14 pages, 1998. https://doi.org/10.1155/1998/38483

Placement and Routing for Performance-Oriented FPGA Layout

Abstract

This paper presents a performance-oriented placement and routing tool for field-programmable gate arrays. Using recursive geometric partitioning for simultaneous placement and global routing, and a graph-based strategy for detailed routing, our tool optimizes source-sink pathlengths, channel width and total wirelength. Our results compare favorably with other FPGA layout tools, as measured by the maximum channel width required to place and route several benchmarks.

Copyright © 1998 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


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