Table of Contents
VLSI Design
Volume 7, Issue 4, Pages 353-364
http://dx.doi.org/10.1155/1998/57380

Performance and Wirability Driven Layout for Row-Based FPGAs

1xilinx Inc., 2100 Logic Drive, San Jose 95124, CA, USA
2Electrical and Computer Engineering, Purdue University, West Lafayette 47907-1285, IN, USA

Received 22 February 1994; Accepted 10 July 1995

Copyright © 1998 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Sudip Nag and Kaushik Roy, “Performance and Wirability Driven Layout for Row-Based FPGAs,” VLSI Design, vol. 7, no. 4, pp. 353-364, 1998. https://doi.org/10.1155/1998/57380.