VLSI Design

VLSI Design / 1998 / Article
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High Performance Design Automation of VLSI Interconnects

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Volume 7 |Article ID 081296 | https://doi.org/10.1155/1998/81296

Kyoung-Son Jhang, Soonhoi Ha, Chu Shik Jhon, "Simulated Annealing Approach to Crosstalk Minimization in Gridded Channel Routing", VLSI Design, vol. 7, Article ID 081296, 11 pages, 1998. https://doi.org/10.1155/1998/81296

Simulated Annealing Approach to Crosstalk Minimization in Gridded Channel Routing

Abstract

The inter-wire spacing in a VLSI chip becomes closer as the VLSI fabrication technology rapidly evolves. Accordingly, it becomes important to minimize crosstalk caused by the coupling capacitance between adjacent wires in the layout design for the fast and safe VLSI circuits. We present a simulated annealing approach based on segment rearrangement to crosstalk minimization in an initially gridded channel routing. The proposed technique is compared with previous track-oriented techniques, especially a track permutation technique whose performance is bounded by an exhaustive track permutation algorithm. Experiments showed that the presented technique is more effective than the track permutation technique.

Copyright © 1998 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


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