François S. Verdier, Bertrand Zavidovique, "A High Level Synthesis System for VLSI Image Processing Applications", VLSI Design, vol. 7, Article ID 095421, 16 pages, 1998. https://doi.org/10.1155/1998/95421
A High Level Synthesis System for VLSI Image Processing Applications
We present a VLSI synthesis environment dedicated to the design of image processing architectures. The environment includes a “front-end” data-flow emulator for validation of the algorithms and the RTL-synthesis system called ALPHA. The latter implements a stochastic search in the design space and produces efficient solutions considering the “restricted” domain of concerned applications. Two simulated Annealing (SA) algorithms run in sequence for data-path synthesis (scheduling and module selection) and then for control synthesis and data-path completion (binding). An interesting feature of the first optimization is the use of the data-flow graph regularity to predict the control influence in terms of the future design. A few designs have already been compiled under this environment including a default detector presented here.
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