A new hierarchical layout vs. schematic (LVS) comparison system for layout verification has been developed. The schematic hierarchy is restructured to remove ambiguities for consistent hierarchical matching. Then the circuit hierarchy is reconstructed from the layout netlist by using a modified SubGemini algorithm recursively in bottom-up fashion. For efficiency, simple gates are found by using a fast rule-based pattern matching algorithm during preprocessing. Experimental results show that our hierarchical netlist comparison technique is effective and efficient in CPU time and in memory usage, especially when the circuit is large and hierarchically structured.