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VLSI Design
Volume 10 (1999), Issue 2, Pages 143-153

Automatic Test Timing Assignment for RAMs Using Linear Programming

1Department of Computer Science, National Tsing-Hua University, Taiwan 300, Hsin-Chu, China
2Vate Technology Co., Ltd., 9 Li-Hsin Rd. V, Science-Based Industrial Park, Taiwan 300, Hsin-Chu, China

Received 23 June 1997; Accepted 24 July 1998

Copyright © 1999 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


In this paper, an automatic technique for test timing assignment is proposed which is comprehensive enough to take the test objective (e.g., strictness of selected AC timing parameters) and the constraints from both RAM specification and tester into consideration. Since test timing assignment problem could only be solved manually before, therefore, our work can significantly reduce the efforts and costs on developing and maintaining timing modules of RAM test programs. In the proposed technique, the test timing assignment problem is transformed into a linear programming (LP) model, which can be automatically solved. Examples of building LP models for an asynchronous DRAM are given to show feasibility of the proposed technique.