VLSI Design

VLSI Design / 1999 / Article
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High Performance Bus-Based Architectures

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Volume 9 |Article ID 079875 | https://doi.org/10.1155/1999/79875

R. Lin, S. Olariu, "Reconfigurable Shift Switching Parallel Comparators", VLSI Design, vol. 9, Article ID 079875, 8 pages, 1999. https://doi.org/10.1155/1999/79875

Reconfigurable Shift Switching Parallel Comparators

Received05 May 1997


We present novel asynchronous VLSI comparator schemes which are based on recently proposed, reconfigurable shift switch logic and the traditional (precharged) CMOS domino logic. The schemes always produce a semaphore as a by-product of the process to indicate the end of domino process, which requires no additional delay and a minimal number of additional devices. For a large percentage of inputs the computations are much faster than traditional synchronous comparators due to the full utilization of the inherent speed of the circuits. Also the schemes are simple, area compact and stable.

Copyright © 1999 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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