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VLSI Design
Volume 9, Issue 1, Pages 83-90
http://dx.doi.org/10.1155/1999/79875

Reconfigurable Shift Switching Parallel Comparators

1Department of Computer Science, SUNY at Geneseo, Geneseo, NY 14454, USA
2Department of Computer Science, Old Dominion University, Norfolk, Va 23529, USA

Received 5 May 1997

Copyright © 1999 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [3 citations]

The following is the list of published articles that have cited the current article.

  • Rong Lin, K. Nakano, S. Olariu, and A.Y. Zomaya, “An efficient VLSI architecture parallel prefix counting with domino logic,” Proceedings 13th International Parallel Processing Symposium and 10th Symposium on Parallel and Distributed Processing. IPPS/SPDP 1999, pp. 273–277, . View at Publisher · View at Google Scholar
  • R. Lin, and S. Olariu, “Efficient VLSI architectures for Columnsort,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 7, no. 1, pp. 135–138, 1999. View at Publisher · View at Google Scholar
  • Rong Lin, K. Nakano, S. Olariu, and A.Y. Zomaya, “An efficient parallel prefix sums architecture with domino logic,” IEEE Transactions on Parallel and Distributed Systems, vol. 14, no. 9, pp. 922–931, 2003. View at Publisher · View at Google Scholar