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VLSI Design
Volume 10 (1999), Issue 1, Pages 35-55
http://dx.doi.org/10.1155/1999/85272

Logic Synthesis for a Regular Layout

1Electrical and Computer Engineering Department, Portland State University, 1800 6th Avenue, Portland 97207-0751, OR, USA
2Lattice Semiconductor Corporation, 5555 NE Moore Count, Hillsboro 97124-0118, OR, USA

Received 7 September 1998; Accepted 20 November 1998

Copyright © 1999 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [3 citations]

The following is the list of published articles that have cited the current article.

  • Jae-Jin Lee, and Gi-Yong Song, “A new application-specific PLD architecture,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol. E88, no. 6, pp. 1425–1432, 2005. View at Publisher · View at Google Scholar
  • Jin S. Zhang, Malgorzata Chrzanowska-Jeske, Alan Misnchenko, and Jerry R. Burch, “Linear cofactor relationships in Boolean functions,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 6, pp. 1011–1023, 2006. View at Publisher · View at Google Scholar
  • Mustafa Altun, and Marc D. Riedel, “Logic synthesis for switching lattices,” IEEE Transactions on Computers, vol. 61, no. 11, pp. 1588–1600, 2012. View at Publisher · View at Google Scholar