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VLSI Design
Volume 9, Issue 2, Pages 147-157
http://dx.doi.org/10.1155/1999/91893

A New Method for Low Power Design of Two-Level Logic Circuits

1VLSI Design Laboratory, Dept. of Electrical and Computer Engineering, University of Patras, Rio 26 110, Greece
2VLSI Design and Testing Center, Laboratory of Electrical & Electronic Materials Technology, Dept. of Electrical and Computer Engineering, Democritus University of Thrace, Xanthi 67 100, Greece

Received 24 March 1997; Accepted 18 January 1998

Copyright © 1999 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

G. Theodoridis, S. Theoharis, D. Soudris, and C. Goutis, “A New Method for Low Power Design of Two-Level Logic Circuits,” VLSI Design, vol. 9, no. 2, pp. 147-157, 1999. https://doi.org/10.1155/1999/91893.