Table of Contents
VLSI Design
Volume 10, Issue 1, Pages 99-116
http://dx.doi.org/10.1155/1999/93607

Analytical Engines are Unnecessary in Top-down Partitioning-based Placement

1IBM Austin Research Laboratory, Austin 78758, TX, USA
2UCLA Computer Science Dept., Los Angeles 90095-1596, CA, USA
3UCLA Mathematics Dept., Los Angeles 90095-1555, CA, USA
4Silicon Perspective Corp., Santa Clara 95054, CA, USA
5UCLA Anderson Graduate School of Management, Los Angeles 90095, CA, USA

Received 7 September 1998; Accepted 20 November 1998

Copyright © 1999 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [4 citations]

The following is the list of published articles that have cited the current article.

  • A. Kennings, and I. Markov, “Analytical minimization of half-perimeter wirelength,” Proceedings 2000. Design Automation Conference. (IEEE Cat. No.00CH37106), pp. 179–184, . View at Publisher · View at Google Scholar
  • Andrew A. Kennings, and Igor L. Markov, “Analytical minimization of half-perimeter wirelength,” Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, pp. 179–184, 2000. View at Publisher · View at Google Scholar
  • Randal E. Bryant, Kwang-Ting Cheng, Kurt Keutzer, Richard Newton, Alberto Sangiovanni-Vincentelli, Andrew B. Kahng, Wojciech Maly, Lawrence Pileggi, and Jan M. Rabaey, “Limitations and challenges of computer-aided design technology for CMOS VLSI,” Proceedings of the IEEE, vol. 89, no. 3, pp. 341–363, 2001. View at Publisher · View at Google Scholar
  • Aa Kennings, and Il Markov, “Smoothening max-terms and analytical minimization of half-perimeter wirelength,” Vlsi Design, vol. 14, no. 3, pp. 229–237, 2002. View at Publisher · View at Google Scholar