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VLSI Design
Volume 10 (2000), Issue 3, Pages 265-279

Reconfigurable Architectures for System Level Applications of Adaptive Computing

University of Southern California, Information Sciences Institute, 4350 N. Fairfax Drive, Suite 770, Arlington 22203, VA, USA

Received 1 February 1999; Accepted 1 October 1999

Copyright © 2000 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [1 citation]

The following is the list of published articles that have cited the current article.

  • R. Rinker, M. Carter, A. Patel, M. Chawathe, C. Ross, J. Hammes, W.A. Najjar, and W. Bohm, “An automated process for compiling dataflow graphs into reconfigurable hardware,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 9, no. 1, pp. 130–139, 2001. View at Publisher ยท View at Google Scholar