Table of Contents
VLSI Design
Volume 11, Issue 3, Pages 175-218

Tutorial on VLSI Partitioning

1Dept. of Electrical Engineering, National Taiwan University, Taipei 10764, Taiwan
2Dept. of Computer Science and Engineering, University of California, San Diego, La Jolla 92093-0114, CA, USA

Received 1 March 1999; Accepted 10 February 2000

Copyright © 2000 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


The tutorial introduces the partitioning with applications to VLSI circuit designs. The problem formulations include two-way, multiway, and multi-level partitioning, partitioning with replication, and performance driven partitioning. We depict the models of multiple pin nets for the partitioning processes. To derive the optimum solutions, we describe the branch and bound method and the dynamic programming method for a special case of circuits. We also explain several heuristics including the group migration algorithms, network flow approaches, programming methods, Lagrange multiplier methods, and clustering methods. We conclude the tutorial with research directions.