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VLSI Design
Volume 11 (2000), Issue 3, Pages 237-248
http://dx.doi.org/10.1155/2000/58485

Circuit Partitioning for FPGAs by the Optimal Circuit Reduction Method

Software Engineering Department Lviv Polytechnic State University, 12 Bandera Street, Lviv 79013, Ukraine

Received 1 March 1999; Accepted 1 December 1999

Copyright © 2000 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [1 citation]

The following is the list of published articles that have cited the current article.

  • Roman Bazylevych, Ihor Podolskyy, and Lubov Bazylevych, “Partitioning optimization by recursive moves of hierarchically built clusters,” Proceedings of the 2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS, pp. 235–238, 2007. View at Publisher ยท View at Google Scholar