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VLSI Design
Volume 11, Issue 3, Pages 237-248
http://dx.doi.org/10.1155/2000/58485

Circuit Partitioning for FPGAs by the Optimal Circuit Reduction Method

Software Engineering Department Lviv Polytechnic State University, 12 Bandera Street, Lviv 79013, Ukraine

Received 1 March 1999; Accepted 1 December 1999

Copyright © 2000 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [5 citations]

The following is the list of published articles that have cited the current article.

  • Roman Bazylevych, and Roman Burtnyk, “Algorithms for software clustering and modularization,” 2015 Xth International Scientific and Technical Conference "Computer Sciences and Information Technologies" (CSIT), pp. 30–33, . View at Publisher · View at Google Scholar
  • Roman Bazylevych, Sergii Byelyayev, Lubov Bazylevych, Alexandr Kolesenkov, Boris Kostrov, Ekaterina Ruchkina, and Vladimir Ruchkin, “The analysis and optimization algorithms of the electronic circuits design,” 2014 3rd Mediterranean Conference on Embedded Computing (MECO), pp. 189–192, . View at Publisher · View at Google Scholar
  • R. Bazylevych, and I. Podolskyy, “Features of the implementation of software package for circuits hierarchical clustering,” Modern Problems of Radio Engineering, Telecommunications and Computer Science (IEEE Cat. No.02EX542), pp. 369–371, . View at Publisher · View at Google Scholar
  • Roman Bazylevych, Marek Palasinski, Lubov Bazylevych, and Dmytro Yanush, “Partitioning optimization by iterative reassignment of the hierarchically built clusters with border elements,” 2013 2nd Mediterranean Conference on Embedded Computing (MECO), pp. 219–222, . View at Publisher · View at Google Scholar
  • Roman Bazylevych, Ihor Podolskyy, and Lubov Bazylevych, “Partitioning optimization by recursive moves of hierarchically built clusters,” Proceedings of the 2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS, pp. 235–238, 2007. View at Publisher · View at Google Scholar