Table of Contents
VLSI Design
Volume 11, Issue 3, Pages 237-248
http://dx.doi.org/10.1155/2000/58485

Circuit Partitioning for FPGAs by the Optimal Circuit Reduction Method

Software Engineering Department Lviv Polytechnic State University, 12 Bandera Street, Lviv 79013, Ukraine

Received 1 March 1999; Accepted 1 December 1999

Copyright © 2000 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

R. P. Bazylevych, R. A. Melnyk, and O. G. Rybak, “Circuit Partitioning for FPGAs by the Optimal Circuit Reduction Method,” VLSI Design, vol. 11, no. 3, pp. 237-248, 2000. https://doi.org/10.1155/2000/58485.