Table of Contents
VLSI Design
Volume 11, Issue 3, Pages 301-310

A New 2-way Multi-level Partitioning Algorithm

Computer Engineering and Computer Science Department, University of Missouri-Columbia, Engineering Building West, Columbia 65211, MO, USA

Received 1 March 1999; Accepted 10 February 2000

Copyright © 2000 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Partitioning is a fundamental problem in the design of VLSI circuits. In recent years, the multi-level partitioning approach has been used with success by a number of researchers. This paper describes a new multi-level partitioning algorithm (PART) that combines a blend of iterative improvement and clustering, biasing of node gains, and local uphill climbs. PART is competitive with recent state-of-the-art partitioning algorithms. PART was able to find new lower cuts for many benchmark circuits. Under suitably mild assumptions, PART also runs in linear time.