Table of Contents
VLSI Design
Volume 10, Issue 3, Pages 321-333

Testing and Diagnosing Dynamic Reconfigurable FPGA

1Lab. for Reliable Computing (Rm. 807), Department of Electrical Engineering, National Tsing Hua University, 101, Sec. 2, Kuang Fu Rd., Taiwan, Hsinchu 30013, China
2Department of Electrical and Computer Engineering, University of California, Santa Barbara 93106, CA, USA

Received 1 February 1999; Accepted 1 October 1999

Copyright © 2000 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [2 citations]

The following is the list of published articles that have cited the current article.

  • N.E. Wu, and Jianhong Ju, “Optimal management of redundant control authority for fault tolerance,” Proceedings of the 2000 American Control Conference. ACC (IEEE Cat. No.00CH36334), pp. 3730–3731vol.6, . View at Publisher · View at Google Scholar
  • Oleg Brekhov, and Maksim Ratnikov, “Pipelined Error-detecting Codes in FPGA Testing,” Advances in Electrical and Computer Engineering, vol. 14, no. 2, pp. 57–62, 2014. View at Publisher · View at Google Scholar