Table of Contents
VLSI Design
Volume 11, Issue 4, Pages 405-415

A Chip for a Routing Table Based on a Novel Modified Trie Algorithm

CINVESTAV del IPN, Research and Advanced Studies Center of National Politechnic Institute, Apartado Postal 31-438, Guadalajara C.P. 44550, Jalisco, Mexico

Received 5 June 1999; Accepted 10 February 2000

Copyright © 2000 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


The design for a routing table circuit for Ethernet-, IP- and ATM-applications is presented. Starting point for the design was an object-oriented general behavior of the routing table. The selected data structure for the routing table is based on a modification of the structure denominated trie, saving one search level and memory space. The architecture for searching and sorting of data, implemented in hardware, is explained. This modified trie stores 64 K addresses and the associated data, achieving a high performance too. The circuit, which can support a flow of 500000 frames/s, is connected to the PCI Bus. For the implementation a FLEX10K100 from Altera Company was used.