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VLSI Design
Volume 11 (2000), Issue 1, Pages 1-21

New Self-dual Circuits for Error Detection and Testing

1University of Potsdam, Department of Computer Science, Fault Tolerant Computing Group, PSF 601553, Potsdam D-14415 , Germany
2Railway Transportation State University, Moskovskij pr. 9, SU190031 St.-Petersburg, Russia

Received 1 April 1999; Accepted 5 October 1999

Copyright © 2000 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


In this paper new methods for the transformation of a given combinational circuit into a self-dual circuit based on the notion of a self-dual complement are investigated. The large variety of self-dual complements can be utilized to optimize the transformed self-dual circuit. Self-dual duplication and self-dual parity prediction are considered in detail. As a method for the reduction of self-dual outputs, output space compaction of self-dual outputs is considered. For the first time we also describe in this paper how a self-dual circuit can be modified into a self-dual fault-secure circuit.