Table of Contents
VLSI Design
Volume 11, Issue 2, Pages 115-128
http://dx.doi.org/10.1155/2000/98945

A Modular and Scalable Architecture for the Realization of High-speed Programmable Rank Order Filters Using Threshold Logic

Worcester Polytechnic Institute, Department of Electrical and Computer Engineering, Worcester 01609-2280, MA, USA

Received 1 June 1999; Accepted 10 November 1999

Copyright © 2000 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

İ. Hatirnaz, F. K. Gürkaynak, and Y. Leblebici, “A Modular and Scalable Architecture for the Realization of High-speed Programmable Rank Order Filters Using Threshold Logic,” VLSI Design, vol. 11, no. 2, pp. 115-128, 2000. https://doi.org/10.1155/2000/98945.