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VLSI Design
Volume 12, Issue 1, Pages 69-79
http://dx.doi.org/10.1155/2001/12026

A Probabilistic Power Estimation Method for Combinational Circuits Under Real Gate Delay Model

1VLSI Design Lab., Dept. of Electrical and Computer Eng., University of Patras, 26110, Greece
2VLSI Design and Testing Center, Dept. of Electrical and Computer Eng., Democritus University of Thrace, Xanthi 67100, Greece

Received 24 September 1999; Revised 6 October 1999

Copyright © 2001 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

G. Theodoridis, S. Theoharis, D. Soudris, and C. Goutis, “A Probabilistic Power Estimation Method for Combinational Circuits Under Real Gate Delay Model,” VLSI Design, vol. 12, no. 1, pp. 69-79, 2001. https://doi.org/10.1155/2001/12026.