VLSI Design

VLSI Design / 2001 / Article
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Computional Electronics; Papers Presented at The Seventh International Workshop on Computional Electronics

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Volume 13 |Article ID 019759 | https://doi.org/10.1155/2001/19759

K. Kalna, A. Asenov, K. Elgaid, I. Thayne, "Scaling of pHEMTs to Decanano Dimensions", VLSI Design, vol. 13, Article ID 019759, 5 pages, 2001. https://doi.org/10.1155/2001/19759

Scaling of pHEMTs to Decanano Dimensions

Abstract

The effect of scaling into deep decanano dimensions on the performance of pseudomorphic high electron mobility transistors (pHEMTs) is extensively studied using Monte Carlo simulations. The scaling of devices with gate lengths of 120, 70, 50 and 30nm is performed in both lateral and vertical directions. The devices exhibit a significant improvement in transconductance during scaling, even though external resistances become a limiting factor.

Copyright © 2001 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


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