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W. B. Jone, D. C. Huang, S. C. Chang, S. R. Das, "Defect Level Estimation for Pseudorandom Testing Using Stochastic Analysis", VLSI Design, vol. 12, Article ID 028741, 18 pages, 2001. https://doi.org/10.1155/2001/28741
Defect Level Estimation for Pseudorandom Testing Using Stochastic Analysis
Pseudorandom testing has been widely used in built-in self-testing of VLSI circuits. Although the defect level estimation for pseudorandom testing has been performed using sequential statical analysis, no closed form can be accomplished as complex combinatorial enumerations are involved. In this work, a Markov model is employed to describe the pseudorandom test behaviors. For the first time, a closed form of the defect level equation is derived by solving the differential equation extracted from the Markov model. The defect level equation clearly describes the relationships among defect level, fabrication yield, the number of all input combinations, circuit detectability (in terms of the worst single stuck-at fault), and pseudorandom test length. The Markov model is then extended to consider all single stuck-at faults, instead of only the worst single stuck-at fault. Results demonstrate that the defect level analysis for pseudorandom testing by only dealing with the worst single stuck-at fault is not adequate (In fact, the worst single stuck-at fault analysis is just a special case). A closed form of the defect level equation is successfully derived to incorporate all single stuck-at faults into consideration. Although our discussions are primarily based on the single struck-at fault model, it is not difficult to extend the results to other fault types.
Copyright © 2001 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.