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VLSI Design
Volume 12 (2001), Issue 4, Pages 457-474

Defect Level Estimation for Pseudorandom Testing Using Stochastic Analysis

1Department of Computer Science and Information Engineering, National Chung-Cheng University, Chiayi, Taiwan
2School of Information Technology and Engineering, University of Ottawa, Ottawa KIN 6N5, Ontario, Canada
3Department of Electrical and Computer Engineering and Computer Science, University of Cincinnati, Cincinnati 45221, OH, USA

Received 15 August 1999; Revised 11 September 2000

Copyright © 2001 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

W. B. Jone, D. C. Huang, S. C. Chang, and S. R. Das, “Defect Level Estimation for Pseudorandom Testing Using Stochastic Analysis,” VLSI Design, vol. 12, no. 4, pp. 457-474, 2001. doi:10.1155/2001/28741