Table of Contents
VLSI Design
Volume 12, Issue 4, Pages 487-500

BIST-Based Fault Diagnosis in the Presence of Embedded Memories

ECE Dept., New Jersey Institute of Technology, University Heights, Newark 07102-1982, New Jersey, USA

Received 15 August 1999; Revised 11 September 2000

Copyright © 2001 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


An efficient method is described for using fault simulation as a solution to the diagnostic problem created by the presence of embedded memories in BIST designs. The simulation is event-table-driven. Special techniques are described to cope with the faults in the Prelogic, Postlogic, and the logic embedding the memory control or address inputs. It is presumed that the memory itself has been previously tested, using automatic test pattern generation (ATPG) techniques via the correspondence inputs, and has been found to be fault-free.