Table of Contents
VLSI Design
Volume 12, Issue 1, Pages 25-52

A Universal, Dynamically Adaptable and Programmable Network Router for Parallel Computers

2ECE and CIS Depts., NJIT, USA
3Department of Electrical and Computer Engineering, New Jersey Institute of Technology, Newark, New Jersey 07102, USA

Received 14 June 1999; Revised 5 January 2000

Copyright © 2001 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [5 citations]

The following is the list of published articles that have cited the current article.

  • Segreen Ingersoll, and Sotirios G. Ziavras, “Dataflow computation with intelligent memories emulated on field-programmable gate arrays (FPGAs),” Microprocessors and Microsystems, vol. 26, no. 6, pp. 263–280, 2002. View at Publisher · View at Google Scholar
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  • Xiaofang Wang, and Sotirios G. Ziavras, “Parallel LU factorization of sparse matrices on FPGA-based configurable computing engines,” Concurrency Computation Practice and Experience, vol. 16, no. 4, pp. 319–343, 2004. View at Publisher · View at Google Scholar
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  • Chung-Ping Young, Chung-Chu Chia, Liang-Bi Chen, and Ing-Jer Huang, “On-chip-network cryptosystem: A high throughput and high security architecture,” IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS, pp. 1276–1279, 2008. View at Publisher · View at Google Scholar