A Size-optimization Design for Variable Length Coding Using Distributed Logic

Abstract

In this paper, we first employ an efficient approach to reduce the time to construct a codeword. With this codeword, a novel VLSI architecture is proposed to realize highspeed Variable Length Coding (VLC). In order to combine with other circuits using cell-based design, we adopt distributed logic rather than memory devices (ROM, PLA) for the implementation. In this architecture, the VLC coding scheme is partitioned into two parts, one is the codeword length and order index for bit control, another is the codeword bank for actual codeword generation. The advantage is that the circuit size of the proposed method can be reduced, where the transistor count of proposed method is only 1/2 and 1/4 of that of ROM- based and PLA-based in average, respectively.