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VLSI Design
Volume 12 (2001), Issue 2, Pages 101-111

A Systematic Approach to Reduce the System Bus Load and Power in Multimedia Algorithms

1lMEC, Kapeldreef 75, Leuven B-3001, Belgium
2lntel Corp., 3600 Juliette Ln., Santa Clara 95052, CA, USA

Received 20 June 2000; Revised 3 August 2000

Copyright © 2001 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Multimedia algorithms deal with enormous amounts of data transfers and storage, resulting in huge bandwidth requirements at the off-chip memory and system bus level. As a result the related energy consumption becomes critical. Even for execution time the bottleneck can shift from the CPU to the external bus load. This paper demonstrates a systematic software approach to reduce this system bus load. It consists of source-to-source code transformations, that have to be applied before the conventional ILP compilation. To illustrate this we use a cavity detection algorithm for medical imaging, that is mapped on an Intel Pentium® II processor.