Table of Contents
VLSI Design
Volume 12, Issue 3, Pages 349-363

Exploiting Data-dependencies in Ultra Low-power DSP Arithmetic

1Dept. of Electronic Systems, University of Westminster, 115 New Cavendish Street, London W1W 6UW, UK
2lHP-GmbH, Frankfurt (Oder), Germany

Received 20 June 2000; Revised 3 August 2000

Copyright © 2001 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Strategies for the design of ultra low power multipliers and multiplier-accumulators are reported. These are optimized for asynchronous applications being able to take advantage of data-dependent computation times. Nevertheless, the low power consumption can be obtained in both synchronous and asynchronous environments. Central to the energy efficiency is a dynamic-logic technique termed Conditional Evaluation which is able to exploit redundancies within the carry-save array and deliver energy consumption which is also heavily data-dependent.

Energy efficient adaptations for handling two's complement operands are introduced. Area overheads of the proposed designs are estimated and transistor level simulation results of signed and unsigned multipliers as well as a signed multiplier-accumulator are given.

Normalized comparisons with other designs show our approach to use less energy than other published multipliers.