Abstract

Transistor folding reduces the area of row-based designs that employ transistors of different size. Kim and Kang [1] have developed an O(m2 log m) algorithm to optimally fold m transistor pairs. In this paper we develop an O(m2) algorithm for optimal transistor folding. Our experiments indicate that our algorithm runs 3 to 60 times as fast for m values in the range (100, 100,000).