Table of Contents
VLSI Design
Volume 15, Issue 3, Pages 557-562

Timing Challenges for Very Deep Sub-Micron (VDSM) IC

1Baynacre, Inc., 1733 Red Maple St., Union City 94587, CA, USA
2Department of Electrical Engineering, Wright State University, Dayton 45435, OH, USA

Received 15 March 2001; Revised 30 January 2002

Copyright © 2002 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Ichiang Lin and Chien-In Henry Chen, “Timing Challenges for Very Deep Sub-Micron (VDSM) IC,” VLSI Design, vol. 15, no. 3, pp. 557-562, 2002.