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VLSI Design
Volume 15 (2002), Issue 2, Pages 547-553

Reduction of Power Dissipation in Dynamic BiCMOS Logic Gates by Transistor Reordering

1Department of Electrical and Computer Engineering, College of Engineering, University of Sharjah, University City, P.O. Box 27272, Sharjah, United Arab Emirates
2Silterra Inc., Kulim High Technology Park, Kulim, Kedah, Malaysia

Received 13 April 2001; Revised 3 May 2002

Copyright © 2002 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


This paper explores the deterministic transistor reordering in low-voltage dynamic BiCMOS logic gates, for reducing the dynamic power dissipation. The constraints of load driving (discharging) capability and NPN turn-on delay for MOSFET reordered structures has been carefully considered. Simulations shows significant reduction in the dynamic power dissipation for the transistor reordered BiCMOS structures. The power-delay product figure-of-merit is found to be significantly enhanced without any associated silicon-area penalty. In order to experimentally verify the reduction in power dissipation, original and reordered structures were fabricated using the MOSIS 2 μm N-well analog CMOS process which has a P-base layer for bipolar NPN option. Measured results shows a 20% reduction in the power dissipation for the transistor reordered structure, which is in close agreement with the simulation.