Table of Contents Author Guidelines Submit a Manuscript
VLSI Design
Volume 15, Issue 2, Pages 547-553
http://dx.doi.org/10.1080/1065514021000012165

Reduction of Power Dissipation in Dynamic BiCMOS Logic Gates by Transistor Reordering

1Department of Electrical and Computer Engineering, College of Engineering, University of Sharjah, University City, P.O. Box 27272, Sharjah, United Arab Emirates
2Silterra Inc., Kulim High Technology Park, Kulim, Kedah, Malaysia

Received 13 April 2001; Revised 3 May 2002

Copyright © 2002 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

S. M. Rezaul Hasan and Yufridin Wahab, “Reduction of Power Dissipation in Dynamic BiCMOS Logic Gates by Transistor Reordering,” VLSI Design, vol. 15, no. 2, pp. 547-553, 2002. https://doi.org/10.1080/1065514021000012165.