Table of Contents
VLSI Design
Volume 15, Issue 3, Pages 619-628

CMOS Delay and Power Model Equations for Simultaneous Transistor and Interconnect Wire Analysis and Optimization

1Agere Systems, 7777 Center Avenue #300, Huntington Beach 92647, CA, USA
2Electrical Department, Arizona State University, Tempe 85287-5706, AZ, USA

Received 15 March 2001; Revised 30 January 2002

Copyright © 2002 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Efficient, generalized delay and power equations are proposed for large scale CMOS circuit analysis and optimization achieved by transistor and interconnect wire minimization. The proposed model equations are used to analyze the entire power-delay trade-off with less complexity and faster computation time. New equations can be adopted to perform the optimization of transistor and interconnect wire size concurrently. A single stage CMOS circuit and a clock generation block fabricated in 0.48 um CMOS process are given as experimental examples.