Abstract
Crosstalk-induced delay in deep sub-micron digital circuits can be quite significant and difficult to determine because of dependency on neighboring signals. In this paper we study the problem of incorporating temporal and functional information to improve the accuracy of crosstalk aware static timing analysis. We propose an efficient method to compute a signal's earliest and latest arrival times when timing windows and slew rate ranges are known for its inputs and its coupling neighbors' inputs. We show that iteratively updating timing windows is necessary when signals on the same path are mutually coupled. The accuracy of static timing analysis can be further improved by our functional correlation analysis. The proposed techniques have been applied in crosstalk aware static timing analysis, which can guide timing-driven layout synthesis and quick timing verification in deep submicron technologies. Experimental results demonstrate that the proposed methods significantly reduce the pessimism in predicting circuit performance.