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VLSI Design
Volume 15, Issue 3, Pages 555-556
http://dx.doi.org/10.1080/1065514021000012174

Timing Analysis and Optimization for DSM IC—Guest Editorial

Department of Electrical Engineering, Wright State University, Dayton 45435, OH, USA

Received 15 March 2001; Revised 30 January 2002

Copyright © 2002 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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