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VLSI Design
Volume 15, Issue 3, Pages 595-604
http://dx.doi.org/10.1080/1065514021000012219

Performance Driven Global Routing Through Gradual Refinement

1Department of EE, Texas A&M University, College Station 77843-3128, TX, USA
2Department of ECE, University of Minnesota, Minneapolis 55455, MN, USA

Received 15 March 2001; Revised 30 January 2002

Copyright © 2002 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Jiang Hu and Sachin S. Sapatnekar, “Performance Driven Global Routing Through Gradual Refinement,” VLSI Design, vol. 15, no. 3, pp. 595-604, 2002. https://doi.org/10.1080/1065514021000012219.