Table of Contents
VLSI Design
Volume 15, Issue 3, Pages 587-594

Simultaneous Buffer-sizing and Wire-sizing for Clock Trees Based on Lagrangian Relaxation

1Department of Electrical and Computer Engineering, University of Wisconsin, Madison 53706, WI, USA
2Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan
3Department of Computer Sciences, University of Texas, Austin 78712, TX, USA

Received 15 March 2001; Revised 30 January 2002

Copyright © 2002 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [3 citations]

The following is the list of published articles that have cited the current article.

  • Subhendu Roy, David Z. Pan, Pavlos M. Mattheakis, Peter S. Colyer, Laurent Masse-Navette, and Pierre-Olivier Ribet, “Skew Bounded Buffer Tree Resynthesis For Clock Power Optimization,” Proceedings of the 25th edition on Great Lakes Symposium on VLSI - GLSVLSI '15, pp. 87–90, . View at Publisher · View at Google Scholar
  • Yuan Xie, Aditya Yanamandra, Soumya Eachempati, Vijaykrishnan Narayanan, and Mary Jane Irwin, “Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution network (Invited Paper),” 2009 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2009, pp. 51–56, 2009. View at Publisher · View at Google Scholar
  • Amin Farshidi, Laleh Behjat, Logan Rakai, and David Westwick, “A Multiobjective Cooptimization of Buffer and Wire Sizes in High-Performance Clock Trees,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 64, no. 4, pp. 412–416, 2017. View at Publisher · View at Google Scholar