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VLSI Design
Volume 15 (2002), Issue 3, Pages 637-645
http://dx.doi.org/10.1080/1065514021000012255

Timing-Driven-Testable Convergent Tree Adders

1LSI Logic Corporation, Milpitas 91436, CA, USA
2Department of Electrical Engineering, Wright State University, Dayton 45435, OH, USA

Received 15 March 2001; Revised 30 January 2002

Copyright © 2002 Hindawi Publishing Corporation. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Johnnie A. Huang and Chien-In Henry Chen, “Timing-Driven-Testable Convergent Tree Adders,” VLSI Design, vol. 15, no. 3, pp. 637-645, 2002. doi:10.1080/1065514021000012255