VLSI Design

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Networks-on-Chip

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Volume 2007 |Article ID 037627 | https://doi.org/10.1155/2007/37627

Srinivasan Murali, David Atienza, Luca Benini, Giovanni De Micheli, "A Method for Routing Packets Across Multiple Paths in NoCs with In-Order Delivery and Fault-Tolerance Gaurantees", VLSI Design, vol. 2007, Article ID 037627, 11 pages, 2007. https://doi.org/10.1155/2007/37627

A Method for Routing Packets Across Multiple Paths in NoCs with In-Order Delivery and Fault-Tolerance Gaurantees

Academic Editor: Maurizio Palesi
Received16 Oct 2006
Revised21 Jan 2007
Accepted06 Feb 2007
Published05 Apr 2007

Abstract

Networks on Chips (NoCs) are required to tackle the increasing delay and poor scalability issues of bus-based communication architectures. Many of today's NoC designs are based on single path routing. By utilizing multiple paths for routing, congestion in the network is reduced significantly, which translates to improved network performance or reduced network bandwidth requirements and power consumption. Multiple paths can also be utilized to achieve spatial redundancy, which helps in achieving tolerance against faults or errors in the NoC. A major problem with multipath routing is that packets can reach the destination in an out-of-order fashion, while many applications require in-order packet delivery. In this work, we present a multipath routing strategy that guarantees in-order packet delivery for NoCs. It is based on the idea of routing packets on partially nonintersecting paths and rebuilding packet order at path reconvergent nodes. We present a design methodology that uses the routing strategy to optimally spread the traffic in the NoC to minimize the network bandwidth needs and power consumption. We also integrate support for tolerance against transient and permanent failures in the NoC links in the methodology by utilizing spatial and temporal redundancy for transporting packets. Our experimental studies show large reduction in network bandwidth requirements (36.86% on average) and power consumption (30.51% on average) compared to single-path systems. The area overhead of the proposed scheme is small (a modest 5% increase in network area). Hence, it is practical to be used in the on-chip domain.

References

  1. L. Benini and G. De Micheli, “Networks on chips: a new SoC paradigm,” IEEE Computer, vol. 35, no. 1, pp. 70–78, 2002. View at: Google Scholar
  2. D. Wingard, “MicroNetwork-based integration for SOCs,” in Proceedings of the 38th Design Automation Conference (DAC '01), pp. 673–677, Las Vegas, Nev, USA, June 2001. View at: Google Scholar
  3. P. Guerrier and A. Greiner, “A generic architecture for on-chip packet-switched interconnections,” in Proceedings of Design, Automation and Test in Europe Conference and Exhibition (DATE '00), pp. 250–256, Paris, France, March 2000. View at: Publisher Site | Google Scholar
  4. K. Goossens, J. Dielissen, O. P. Gangwal, S. G. Pestana, A. Rădulescu, and E. Rijpkema, “A design flow for application-specific networks on chip with guaranteed performance to accelerate SOC design and verification,” in Proceedings of Design, Automation and Test in Europe Conference and Exhibition (DATE '05), vol. 2, pp. 1182–1187, Munich, Germany, March 2005. View at: Publisher Site | Google Scholar
  5. S. Kumar, A. Jantsch, J.-P. Soininen et al., “A network on chip architecture and design methodology,” in Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI '02), pp. 105–112, Pittsburgh, Pa, USA, April 2002. View at: Publisher Site | Google Scholar
  6. F. Karim, A. Nguyen, S. Dey, and R. Rao, “On-chip communication architecture for OC-768 network processors,” in Proceedings of the 38th Design Automation Conference (DAC '01), pp. 678–683, Las Vegas, Nev, USA, June 2001. View at: Google Scholar
  7. D. Bertozzi, A. Jalabert, S. Murali et al., “NoC synthesis flow for customized domain specific multi-processor systems-on-chip,” IEEE Transactions on Parallel and Distributed Systems, vol. 16, no. 2, pp. 113–129, 2005. View at: Publisher Site | Google Scholar
  8. H. Jingcao and R. Marculescu, “Exploiting the routing flexibility for energy/performance aware mapping of regular NoC architectures,” in Proceedings of Design, Automation and Test in Europe Conference and Exhibition (DATE '03), pp. 688–693, Munich, Germany, March 2003. View at: Google Scholar
  9. F. Angiolini, P. Meloni, S. Carta, L. Benini, and L. Raffo, “Contrasting a NoC and a traditional interconnect fabric with layout awareness,” in Proceedings of Design, Automation and Test in Europe (DATE '06), vol. 1, pp. 124–129, Munich, Germany, March 2006. View at: Google Scholar
  10. V. Karamcheti and A. A. Chien, “Do faster routers imply faster communication?” in Proceedings of the 1st International Workshop on Parallel Computer Routing and Communication (PCRCW '94), vol. 853 of Lecture Notes in Computer Science, pp. 1–15, Springer, Seattle, Wash, USA, May 1994. View at: Google Scholar
  11. S. Murali, T. Theocharides, N. Vijaykrishnan, M. J. Irwin, L. Benini, and G. De Micheli, “Analysis of error recovery schemes for networks on chips,” IEEE Design and Test of Computers, vol. 22, no. 5, pp. 434–442, 2005. View at: Publisher Site | Google Scholar
  12. S. Murali and G. De Micheli, “Bandwidth-constrained mapping of cores onto NoC architectures,” in Proceedings of Design, Automation and Test in Europe Conference and Exhibition (DATE '04), vol. 2, pp. 896–901, Paris, France, February 2004. View at: Google Scholar
  13. A. Hansson, K. Goossens, and A. Rădulescu, “A unified approach to constrained mapping and routing on network-on-chip architectures,” in Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and Systems Synthesis (CODES+ISSS '05), pp. 75–80, Jersey City, NJ, USA, September 2005. View at: Google Scholar
  14. S. Murali, L. Benini, and G. De Micheli, “Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees,” in Proceedings of the 12th Asia and South Pacific Design Automation Conference (ASP-DAC '05), pp. 27–32, Shanghai, China, January 2005. View at: Google Scholar
  15. S. Murali and G. De Micheli, “SUNMAP: a tool for automatic topology selection and generation for NoCs,” in Proceedings of Design Automation Conference (DAC '04), pp. 914–919, San Diego, Calif, USA, June 2004. View at: Google Scholar
  16. J. Kim, D. Park, T. Theocharides, N. Vijaykrishnan, and C. R. Das, “A low latency router supporting adaptivity for on-chip interconnects,” in Proceedings of the 42nd Design Automation Conference (DAC '05), pp. 559–564, Anaheim, Calif, USA, June 2005. View at: Google Scholar
  17. H. Jingcao and R. Marculescu, “DyAD - smart routing for networks-on-chip,” in Proceedings of the 41st Design Automation Conference (DAC '04), pp. 260–263, San Diego, Calif, USA, June 2004. View at: Google Scholar
  18. W. J. Dally and B. Towles, Principles and Practices of Interconnection Networks, Morgan Kaufmann, San Francisco, Calif, USA, 2003.
  19. W. J. Dally, P. P. Carvey, and L. R. Dennison, “Architecture of the avici terabit switch/router,” in Proceedings of Hot-Interconnects VI, pp. 41–50, Stanford, Calif, USA, August 1998. View at: Google Scholar
  20. C. B. Stunkel, D. G. Shea, B. Abali et al., “The SP2 communication subsystem,” Tech. Rep., IBM, Yorktown Heights, NY, USA, August 1994. View at: Google Scholar
  21. Y. Aydogan, C. B. Stunkel, C. Aykanat, and B. Abali, “Adaptive source routing in multistage interconnection networks,” in Proceedings of the 10th International Parallel Processing Symposium (IPPS '96), pp. 258–267, Honolulu, Hawaii, USA, April 1996. View at: Publisher Site | Google Scholar
  22. R. Hegde and N. R. Shanbhag, “Towards achieving energy-efficiency in presence of deep submicron noise,” IEEE Transactions on VLSI Systems, vol. 8, no. 4, pp. 379–391, 2000. View at: Publisher Site | Google Scholar
  23. D. Bertozzi, L. Benini, and G. De Micheli, “Error control schemes for on-chip communication links: the energy-reliability tradeoff,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 6, pp. 818–831, 2005. View at: Publisher Site | Google Scholar
  24. R. Marculescu, “Networks-on-chip: the quest for on-chip fault-tolerant communication,” in Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI '03), pp. 8–12, Tampa, Fla, USA, February 2003. View at: Google Scholar
  25. H. Zimmer and A. Jantsch, “A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip,” in Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '03), pp. 188–193, Newport Beach, Calif, USA, October 2003. View at: Google Scholar
  26. F. Worm, P. Thiran, P. Ienne, and G. De Micheli, “An adaptive low-power transmission scheme for on-chip networks,” in Proceedings of the 15th International Symposium on System Synthesis (ISSS '02), pp. 92–100, Kyoto, Japan, October 2002. View at: Google Scholar
  27. M. Pirretti, G. M. Link, R. R. Brooks, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin, “Fault tolerant algorithms for network-on-chip interconnect,” in Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI '04), pp. 46–51, Lafayette, La, USA, February 2004. View at: Google Scholar
  28. S. Manolache, P. Eles, and Z. Peng, “Fault and energy-aware communication mapping with guaranteed latency for applications implemented on NoC,” in Proceedings of the 42nd Design Automation Conference (DAC '05), pp. 266–269, Anaheim, Calif, USA, June 2005. View at: Google Scholar
  29. S. Murali, D. Atienza, L. Benini, and G. De Micheli, “A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip,” in Proceedings of the 43rd ACM/IEEE Design Automation Conference (DAC '06), pp. 845–848, San Francisco, Calif, USA, July 2006. View at: Google Scholar
  30. M. Palesi, R. Holsmark, S. Kumar, and V. Catania, “A methodology for design of application specific deadlock-free routing algorithms for NoC systems,” in Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS '06), pp. 142–147, Seoul, Korea, October 2006. View at: Google Scholar
  31. T. H. Cormen, C. E. Leiserson, and R. L. Rivest, Introduction to Algorithms, The MIT Press, Cambridge, Mass, USA, 1990.
  32. G. De Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill, New York, NY, USA, 1994.
  33. http://www.ocpip.org/.

Copyright © 2007 Srinivasan Murali et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


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