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VLSI Design
Volume 2007 (2007), Article ID 42829, 8 pages
http://dx.doi.org/10.1155/2007/42829
Research Article

Power Consumption and BER of Flip-Flop Inserted Global Interconnect

Department of Electrical and Computer Engineering, University of Illinois at Chicago, Chicago 60607, IL, USA

Received 23 October 2006; Revised 14 March 2007; Accepted 2 April 2007

Academic Editor: Bernard Courtois

Copyright © 2007 Jingye Xu et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

In nanometer scale integrated circuits, concurrent insertion of repeaters and sequential elements into the global interconnect lines has been proposed to support multicycle communication—a concept known as interconnect pipelining. The design targets of an interconnect-pipelining scheme are to ensure high reliability, low-power consumption, and less delay cycles. This paper presents an in-depth analysis of the reliability in terms of bit error rate (BER) and the power consumption of wire-pipelining scheme. In this analysis, the dependencies of power consumption and BER on the number of inserted flip-flops, and the size of repeaters are illustrated. To trade off the design targets (wire delay, BER, and power consumption), a methodology is developed to optimize the repeater size and the number of flip-flops inserted which maximize a user-specified figure of merit. The methodology is demonstrated by calculating optimal solutions for interconnect pipelining for some International Technology Roadmap for Semiconductor technology nodes.