Table of Contents Author Guidelines Submit a Manuscript
VLSI Design
Volume 2007 (2007), Article ID 42829, 8 pages
http://dx.doi.org/10.1155/2007/42829
Research Article

Power Consumption and BER of Flip-Flop Inserted Global Interconnect

Department of Electrical and Computer Engineering, University of Illinois at Chicago, Chicago 60607, IL, USA

Received 23 October 2006; Revised 14 March 2007; Accepted 2 April 2007

Academic Editor: Bernard Courtois

Copyright © 2007 Jingye Xu et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. “International Technology Roadmap for Semiconductors,” Semiconductor Research Corporation, 2004.
  2. V. Nookala and S. S. Sapatnekar, “Designing optimized pipelined global interconnects: algorithms and methodology impact,” in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS '05), vol. 1, pp. 608–611, Kobe, Japan, May 2005. View at Publisher · View at Google Scholar
  3. J. Cong, Y. Fan, and Z. Zhang, “Architecture-level synthesis for automatic interconnect pipelining,” in Proceedings of the 41st Design Automation Conference (DAC '04), pp. 602–607, San Diego, Calif, USA, June 2004.
  4. L. Scheffer, “Methodologies and tools for pipelined on-chip interconnect,” in Proceedings of IEEE International Conference on Computer Design: VLSI in Computers and Processors, pp. 152–157, Freiburg, Germany, September 2002. View at Publisher · View at Google Scholar
  5. A. Jagannathan, H. H. Yang, and K. Konigsfeld et al., “Microarchitecture evaluation with floorplanning and interconnect pipelining,” in Proceedings of the Design Automation Conference (DAC '05), vol. 1, pp. 8–15, Anaheim, Calif, USA, June 2005. View at Publisher · View at Google Scholar
  6. H. Zhou and C. Lin, “Retiming for wire pipelining in system-on-chip,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 23, no. 9, pp. 1338–1345, 2004. View at Publisher · View at Google Scholar
  7. V. Nookala and S. S. Sapatnekar, “A method for correcting the functionality of a wire-pipelined circuit,” in Proceedings of the 41st Design Automation Conference (DAC '04), pp. 570–575, San Diego, Calif, USA, June 2004.
  8. M. R. Casu and L. Macchiarulo, “A new approach to latency insensitive design,” in Proceedings of the 41st Design Automation Conference (DAC '04), pp. 576–581, San Diego, Calif, USA, June 2004.
  9. L. Zhang, Y. Hu, and C. C.-P. Chen, “Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining,” in Proceedings of the 41st Design Automation Conference (DAC '04), pp. 904–907, San Diego, Calif, USA, June 2004.
  10. V. Seth, M. Zhao, and J. Hu, “Exploiting level sensitive latches in wire pipelining,” in Proceedings of IEEE/ACM International Conference on Computer Aided Design (ICCAD '04), pp. 283–290, San Jose, Calif, USA, November 2004.
  11. J. Xu and M. H. Chowdhury, “Latch based interconnect pipelining for high speed integrated circuits,” in Proceedings of the 6th IEEE International Conference on Electro/Information Technology (EIT '06), pp. 295–300, East Lansing, Mich, USA, May 2006. View at Publisher · View at Google Scholar
  12. R. Lu, G. Zhong, C.-K. Koh, and K.-Y. Chao, “Flip-flop and repeater insertion for early interconnect planning,” in Proceedings of Design, Automation and Test in Europe Conference and Exhibition, pp. 690–695, Paris, France, March 2002. View at Publisher · View at Google Scholar
  13. W. Liao and L. He, “Full-chip interconnect power estimation and simulation considering concurrent repeater and flip-flop insertion,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD '03), pp. 574–580, San Jose, Calif, USA, November 2003.
  14. W. Liao and L. He, “Full-chip interconnect power estimation and simulation considering concurrent repeater and flip-flop insertion,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD '03), pp. 574–580, San Jose, Calif, USA, November 2003.
  15. V. Adler and E. G. Friedman, “Repeater design to reduce delay and power in resistive interconnect,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 45, no. 5, pp. 607–616, 1998. View at Publisher · View at Google Scholar
  16. K. Banerjee and A. Mehrotra, “A power-optimal repeater insertion methodology for global interconnects in nanometer designs,” IEEE Transactions on Electron Devices, vol. 49, no. 11, pp. 2001–2007, 2002. View at Publisher · View at Google Scholar
  17. X.-C. Li, J.-F. Mao, H.-F. Huang, and Y. Liu, “Global interconnect width and spacing optimization for latency, bandwidth and power dissipation,” IEEE Transactions on Electron Devices, vol. 52, no. 10, pp. 2272–2279, 2005. View at Publisher · View at Google Scholar
  18. M. L. Mui, K. Banerjee, and A. Mehrotra, “A global interconnect optimization scheme for nanometer scale VLSI with implications for latency, bandwidth, and power dissipation,” IEEE Transactions on Electron Devices, vol. 51, no. 2, pp. 195–203, 2004. View at Publisher · View at Google Scholar
  19. A. G. M. Strollo, E. Napoli, and C. Cimino, “Analysis of power dissipation in double edge-triggered flip-flops,” IEEE Transactions on Very Large Scale Integration Systems, vol. 8, no. 5, pp. 624–629, 2000. View at Publisher · View at Google Scholar
  20. M. L. Mui, K. Banerjee, and A. Mehrotra, “A global interconnect optimization scheme for nanometer scale VLSI with implications for latency, bandwidth, and power dissipation,” IEEE Transactions on Electron Devices, vol. 51, no. 2, pp. 195–203, 2004. View at Publisher · View at Google Scholar
  21. H. B. Bakoglu, Circuits, Interconnections and Packaging for VLSI, Addision-Wesley, Reading, Mass, USA, 1990.