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VLSI Design
Volume 2007 (2007), Article ID 45269, 13 pages
Research Article

Flexible Architecture of Ultra-Low-Power Current-Mode Interleaved Successive Approximation Analog-to-Digital Converter for Wireless Sensor Networks

1Institute of Microtechnology, University of Neuchâtel, Rue A.-L. Breguet 2, Neuchâtel CH-2000, Switzerland
2Department of Electrical and Computer Engineering, University of Alberta, Edmonton, AB, Canada T6G 2V4
3CMOS Emerging Technologies Inc., 2865 Stanley Place, Coquitlam, BC, Canada V3B 7L7

Received 31 October 2006; Accepted 21 April 2007

Academic Editor: Wieslaw Kuzmicz

Copyright © 2007 Rafał Długosz and K. Iniewski. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


A novel 8-bit current mode interleaved successive approximation (SAR) analog-digital converter (ADC) has been proposed. The proposed converter architecture is very flexible. Using two control DC voltages and one reference current, the converter can be tuned to work with different sampling rates, number of bits of resolution, and power consumption levels. Due to its very low-power consumption and flexibility, the converter is particularly suitable for application in wireless sensor networks. Compared to other solutions presented in the literature, the proposed converter achieves very high figure of merit (FOM) value due to numerous low-power circuit innovations utilized in its design. The circuit has been implemented in CMOS 0.18 μm technology. Minimum energy consumption has been found to be in a 25–250 kS/s range (for clock sampling frequency in a 200 kHz--2 MHz range) for a single SAR section with the corresponding power dissipation varying from 220 nW to 560 nW for 0.55 V power supply.