Table of Contents Author Guidelines Submit a Manuscript
VLSI Design
Volume 2007 (2007), Article ID 46514, 13 pages
Research Article

High-Performance Long NoC Link Using Delay-Insensitive Current-Mode Signaling

1Department of Information Technology, University of Turku, Turku 20014, Finland
2Turku Centre for Computer Science (TUCS), Turku 20520, Finland
3Research Council for Natural Sciences and Engineering, Academy of Finland, Helsinki 00501, Finland

Received 1 November 2006; Revised 24 January 2007; Accepted 1 March 2007

Academic Editor: Maurizio Palesi

Copyright © 2007 Ethiopia Nigussie et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. U. Y. Ogras and R. Marculescu, ““It's a small world after all”: NoC performance optimization via long-range link insertion,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 14, no. 7, pp. 693–706, 2006. View at Publisher · View at Google Scholar
  2. W. J. Dally and B. P. Towles, Principles and Practices of Interconnection Networks, Morgan Kaufmann-Elsevier, San Francisco, Calif, USA, 2004.
  3. W. J. Dally and B. Towles, “Route packets, not wires: on-chip interconnection networks,” in Proceedings of the 38th Design Automation Conference (DAC '01), pp. 684–689, Las Vegas, Nev, USA, June 2001.
  4. D. Sylvester and K. Keutze, “A global wiring paradigm for deep submicron design,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 19, no. 2, pp. 242–252, 2000. View at Publisher · View at Google Scholar
  5. S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, and V. De, “Parameter variations and impact on circuits and microarchitecture,” in Proceedings of the 40th Design Automation Conference (DAC '03), pp. 338–342, Anaheim, Calif, USA, June 2003.
  6. R. Ho, J. Gainsley, and R. Drost, “Long wires and asynchronous control,” in Proceedings of the 10th International Symposium on Asynchronous Circuits and Systems (ASYNC '04), pp. 240–249, Crete, Greece, April 2004.
  7. T. Verhoeff, “Delay-insensitive codes—an overview,” Distributed Computing, vol. 3, no. 1, pp. 1–8, 1988. View at Publisher · View at Google Scholar
  8. W. J. Dally and J. W. Poulton, Digital Systems Engineering, Cambridge University Press, Cambridge, UK, 1998.
  9. D. Pamunuwa and H. Tenhunen, “Repeater insertion to minimise delay in coupled interconnects,” in Proceedings of the 14th IEEE International Conference on VLSI Design, pp. 513–517, Bangalore, India, January 2001.
  10. R. Bashirullah, W. Liu, and R. K. Cavin III, “Current-mode signaling in deep submicrometer global interconnects,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 11, no. 3, pp. 406–417, 2003. View at Publisher · View at Google Scholar
  11. A. Katoch, E. Seevinck, and H. Veendrick, “Fast signal propagation for point to point on-chip long interconnects using current sensing,” in Proceedings of the 28th European Solid-State Circuits Conference (ESSCIRC '02), pp. 195–198, Florence, Italy, September 2002.
  12. A. Katoch, H. Veendrick, and E. Seevinick, “High speed current-mode signaling circuits for on-chip interconnects,” in Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS '05), vol. 4, pp. 4138–4141, Kobe, Japan, May 2005.
  13. A. P. Jose, G. Patounakis, and K. L. Shepard, “Near speed-of-light on-chip interconnects using pulsed current-mode signalling,” in Proceedings of IEEE Symposium on VLSI Circuits Digest of Technical Papers, pp. 108–111, Kyoto, Japan, June 2005. View at Publisher · View at Google Scholar
  14. M. K. Gowan, L. L. Biro, and D. B. Jackson, “Power considerations in the design of the Alpha 21264 microprocessor,” in Proceedings of the 35th Design Automation Conference (DAC '98), pp. 726–731, San Francisco, Calif, USA, June 1998.
  15. R. Bashirullah, “Reduced delay sensitivity to process induced variability in current sensing interconnects,” Electronics Letters, vol. 42, no. 9, pp. 531–532, 2006. View at Publisher · View at Google Scholar
  16. J. Q. Zhang, S. I. Long, F. H. Ho, and J. K. Madsen, “Low power current mode multi-valued logic interconnect for high speed interchip communications,” in Proceedings of the 17th Annual IEEE Gallium Arsenide Integrated Circuit Symposium (GaAs IC '95), pp. 327–330, San Diego, Calif, USA, October-November 1995.
  17. J.-Y. Sim, Y.-S. Sohn, S.-C. Heo, H.-J. Park, and S.-I. Cho, “A 1-Gb/s bidirectional I/O buffer using the current-mode scheme,” IEEE Journal of Solid-State Circuits, vol. 34, no. 4, pp. 529–535, 1999. View at Publisher · View at Google Scholar
  18. I. B. Dhaou, M. Ismail, and H. Tenhunen, “Current mode, low-power, on-chip signaling in deep-submicron CMOS technology,” IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 50, no. 3, pp. 397–406, 2003. View at Publisher · View at Google Scholar
  19. T. Temel and A. Morgul, “Implementation of multi-valued logic gates using full current-mode CMOS circuits,” Analog Integrated Circuits and Signal Processing, vol. 39, no. 2, pp. 191–204, 2004. View at Publisher · View at Google Scholar
  20. T. Hanyu, T. Takahashi, and M. Kameyama, “Bidirectional data transfer based asynchronous VLSI system using multiple-valued current mode logic,” in Proceedings of the 33rd International Symposium on Multiple-Valued Logic, pp. 99–104, Tokyo, Japan, May 2003.
  21. E. Nigussie, J. Plosila, and J. Isoaho, “Delay-insensitive on-chip communication link using low-swing simultaneous bidirectional signaling,” in Proceedings of IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures, pp. 217–222, Karlsruhe, Germany, March 2006. View at Publisher · View at Google Scholar
  22. V. Venkatraman and W. Burleson, “Robust multi-Level current-mode on-chip interconnect signaling in the presence of process variations,” in Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED '05), pp. 522–527, San Jose, Calif, USA, March 2005.
  23. R. Venkatesan, J. A. Davis, and J. D. Meindl, “Compact distributed RLC interconnect models—part IV: unified models for time delay, crosstalk, and repeater insertion,” IEEE Transactions on Electron Devices, vol. 50, no. 4, pp. 1094–1102, 2003. View at Publisher · View at Google Scholar
  24. Y. I. Ismail, E. G. Friedman, and J. L. Neves, “Figures of merit to characterize the importance of on-chip inductance,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 7, no. 4, pp. 442–449, 1999. View at Publisher · View at Google Scholar
  25. M. Kamon, M. J. Tsuk, and J. K. White, “FASTHENRY: a mutipole-accelerated 3-D inductance extraction program,” IEEE Transactions on Microwave Theory and Techniques, vol. 42, no. 9, pp. 1750–1758, 1994. View at Publisher · View at Google Scholar
  26. A. R. Djordjevic, M. B. Bazdar, T. K. Sarkar, and R. F. Harrington, Linpar for Windows: matrix parameters for multiconductor transmission lines, Software and User Manual, Version 2.0, Artech House Publisher, Norwood, Mass, USA, 1999.
  27. International Technology Roadmap for Semiconductors, 2005,