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VLSI Design
Volume 2007 (2007), Article ID 58431, 7 pages
Research Article

A Video Specific Instruction Set Architecture for ASIP design

Institute of Microelectronics, Tsinghua University, Beijing 100084, China

Received 9 May 2007; Revised 2 August 2007; Accepted 14 September 2007

Academic Editor: Sheldon Tan

Copyright © 2007 Zheng Shen et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


This paper describes a novel video specific instruction set architecture for ASIP design. With single instruction multiple data (SIMD) instructions, two destination modes, and video specific instructions, an instruction set architecture is introduced to enhance the performance for video applications. Furthermore, we quantify the improvement on H.263 encoding. In this paper, we evaluate and compare the performance of VS-ISA, other DSPs (digital signal processors), and conventional SIMD media extensions in the context of video coding. Our evaluation results show that VS-ISA improves the processor's performance by approximately 5x on H.263 encoding, and VS-ISA outperforms other architectures by 1.6x to 8.57x in computing IDCT.