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VLSI Design
Volume 2007 (2007), Article ID 71974, 13 pages
Research Article

Low-Power Fully Integrated CMOS DTV Tuner Front-End for ATSC Terrestrial Broadcasting

Analog and Mixed Signal Center, Department of Electrical and Computer Engineering, Texas A&M University, College Station 77843-3128, TX, USA

Received 7 September 2006; Revised 15 December 2006; Accepted 19 December 2006

Academic Editor: Adoracion Rueda

Copyright © 2007 Jianhong Xiao et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


A low-cost low-power DTV tuner for current digital television application is described. In order to increase integration level and reduce power consumption for off-air DTV tuner application, an SAW-filterless tuner front-end architecture is adopted. As a part of the concept, key building blocks for this architecture are implemented on a main stream 0.35 μm CMOS technology. Experimental measurements for the prototype chip validate the system architecture; the prototype consumes 300 mw and achieves 45 dB of image rejection ratio within the entire 750 MHz frequency band.