Eight-Bit Semiflash A/D Converter

Dimitrov, D. P.; Vasileva, T. K.

doi:https://doi.org/10.1155/2007/80389

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Research Article | Open Access

Volume 2007 | Article ID 080389 | https://doi.org/10.1155/2007/80389

Eight-Bit Semiflash A/D Converter

D. P. Dimitrov¹and T. K. Vasileva²

Academic Editor: Andrzej Napieralski

Received16 Nov 2006

Accepted15 Jun 2007

Published12 Jul 2007

Abstract

An 8-bit semiflash ADC is reported that uses a single array of 15 comparators for both the coarse and the fine conversion. Conversion is implemented in two steps. First, an estimate is made of the 4 most significant bits, which are then memorized in the output latch. Next, the remaining 4 bits are evaluated by the same array of comparators. The auto-zeroed comparators also perform the function of a sample-and-hold circuit. In the proposed 8-bit semiflash ADC, there are no sample-and-hold circuit, no DAC, no subtraction circuit, and no residue amplifier. As a result, a moderate conversion speed has been combined with a drastically reduced power consumption. The ADC was fabricated in a standard 0.6 μm double-poly, double-metal CMOS process. Experimental results show monotonic conversion with very low integral and differential nonlinearities. These features, combined with the ultra-low power consumption, make the proposed circuit very suitable for low-power mixed-signal applications.

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Copyright

Copyright © 2007 D. P. Dimitrov and T. K. Vasileva. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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