Table of Contents Author Guidelines Submit a Manuscript
VLSI Design
Volume 2007 (2007), Article ID 80389, 7 pages
Research Article

Eight-Bit Semiflash A/D Converter

1Melexis, Bulgaria Ltd, Bulgaria
2Technical University of Sofia, Bulgaria

Received 16 November 2006; Accepted 15 June 2007

Academic Editor: Andrzej Napieralski

Copyright © 2007 D. P. Dimitrov and T. K. Vasileva. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


An 8-bit semiflash ADC is reported that uses a single array of 15 comparators for both the coarse and the fine conversion. Conversion is implemented in two steps. First, an estimate is made of the 4 most significant bits, which are then memorized in the output latch. Next, the remaining 4 bits are evaluated by the same array of comparators. The auto-zeroed comparators also perform the function of a sample-and-hold circuit. In the proposed 8-bit semiflash ADC, there are no sample-and-hold circuit, no DAC, no subtraction circuit, and no residue amplifier. As a result, a moderate conversion speed has been combined with a drastically reduced power consumption. The ADC was fabricated in a standard 0.6 μm double-poly, double-metal CMOS process. Experimental results show monotonic conversion with very low integral and differential nonlinearities. These features, combined with the ultra-low power consumption, make the proposed circuit very suitable for low-power mixed-signal applications.