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VLSI Design
Volume 2007 (2007), Article ID 95402, 12 pages
http://dx.doi.org/10.1155/2007/95402
Research Article

Variation-Tolerant and Low-Power Source-Synchronous Multicycle On-Chip Interconnect Scheme

Maged Ghoneima,1 Yehea Ismail,2 Muhammad Khellah,3 and Vivek De3

1VLSI Design Group, NVIDIA Corporation, Santa Clara 95050, CA, USA
2Electrical Enginering and Computer Science Department (EECS), Northwestern University, Evanston, 60208-3118, IL, USA
3Circuit Research Laboratories, Intel Corporation, Hillsboro 97124, OR, USA

Received 6 November 2006; Revised 27 February 2007; Accepted 16 March 2007

Academic Editor: Davide Bertozzi

Copyright © 2007 Maged Ghoneima et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

A variation-tolerant low-power source-synchronous multicycle (SSMC ) interconnect scheme is proposed. This scheme is scalable and suitable for transferring data across different clock domains such as those in “many-core” SoCs and in 3D-ICs. SSMC replaces intermediate flip-flops by a source-synchronous synchronization scheme. Removing the intermediate flip-flops in the SSMC scheme enables better averaging of delay variations across the whole interconnect, which reduces bit-rate degradation due to within-die WID process variations. Monte Carlo circuit simulations show that SSMC eliminates 90% of the variation-induced performance degradation in a 6-cycle 9 mm-long 16-bit conventional bus. The proposed multicycle bus scheme also leads to significant energy savings due to eliminating the power-hungry flip-flops and efficiently designing the source synchronization overhead. Moreover, eliminating intermediate flip-flops avoids the timing overhead of the setup time, the flip-flop delay, and the single-cycle clock jitter. This delay slack can then be translated into further energy savings by downsizing the repeaters. The significant delay jitter due to capacitive coupling has been addressed and solutions are put forward to alleviate it. Circuit simulations in a  65-nm process environment indicate that energy savings up to 20% are achievable for a 6-cycle 9 mm long 16-bit bus.