Variation-Tolerant and Low-Power Source-Synchronous Multicycle On-Chip Interconnect Scheme

Ghoneima, Maged; Ismail, Yehea; Khellah, Muhammad; De, Vivek

doi:https://doi.org/10.1155/2007/95402

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Networks-on-Chip

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Research Article | Open Access

Volume 2007 | Article ID 095402 | https://doi.org/10.1155/2007/95402

Variation-Tolerant and Low-Power Source-Synchronous Multicycle On-Chip Interconnect Scheme

Maged Ghoneima,¹Yehea Ismail,²Muhammad Khellah,³and Vivek De³

Academic Editor: Davide Bertozzi

Received06 Nov 2006

Revised27 Feb 2007

Accepted16 Mar 2007

Published02 Jul 2007

Abstract

A variation-tolerant low-power source-synchronous multicycle (SSMC ) interconnect scheme is proposed. This scheme is scalable and suitable for transferring data across different clock domains such as those in “many-core” SoCs and in 3D-ICs. SSMC replaces intermediate flip-flops by a source-synchronous synchronization scheme. Removing the intermediate flip-flops in the SSMC scheme enables better averaging of delay variations across the whole interconnect, which reduces bit-rate degradation due to within-die WID process variations. Monte Carlo circuit simulations show that SSMC eliminates 90% of the variation-induced performance degradation in a 6-cycle 9 mm-long 16-bit conventional bus. The proposed multicycle bus scheme also leads to significant energy savings due to eliminating the power-hungry flip-flops and efficiently designing the source synchronization overhead. Moreover, eliminating intermediate flip-flops avoids the timing overhead of the setup time, the flip-flop delay, and the single-cycle clock jitter. This delay slack can then be translated into further energy savings by downsizing the repeaters. The significant delay jitter due to capacitive coupling has been addressed and solutions are put forward to alleviate it. Circuit simulations in a 65-nm process environment indicate that energy savings up to 20% are achievable for a 6-cycle 9 mm long 16-bit bus.

References

J. D. Meindl, J. A. Davis, P. Zarkesh-Ha, C. S. Patel, K. P. Martin, and P. A. Kohl, “Interconnect opportunities for gigascale integration,” IBM Journal of Research and Development, vol. 46, no. 2-3, pp. 245–263, 2002.
View at: Google Scholar
K. Rahmat, S. Nakagawa, S-Y. Oh, and J. Moll, “A scaling scheme for interconnects in deep-submicron processes,” Tech. Rep. HPL-95-77, Hewlett Packard, Palo Alto, Calif, USA, 1995.
View at: Google Scholar
L. P. Carloni, K. L. McMillan, and A. L. Sangiovanni-Vincentelli, “Theory of latency-insensitive design,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 20, no. 9, pp. 1059–1076, 2001.
View at: Publisher Site | Google Scholar
L. Scheffer, “Methodologies and tools for pipelined on-chip interconnect,” in Proceedings of IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD '02), pp. 152–157, Freiburg, Germany, September 2002.
View at: Publisher Site | Google Scholar
R. Lu, G. Zhong, C.-K. Koh, and K.-Y. Chao, “Flip-flop and repeater insertion for early interconnect planning,” in Proceedings of the Design, Automation and Test in Europe Conference (DATE '02), pp. 690–695, Paris, France, March 2002.
View at: Publisher Site | Google Scholar
P. Cocchini, “Concurrent flip-flop and repeater insertion for high performance integrated circuits,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD '02), pp. 268–273, San Jose, Calif, USA, November 2002.
View at: Publisher Site | Google Scholar
“IEEE 1149.1-2001: Standard Test Access Port and Boundary-Scan Architecture,” Institute of Electrical and Electronics Engineers.
View at: Google Scholar
M. Khellah, M. Ghoneima, and J. Tschanz et al., “A skewed repeater bus architecture for on-chip energy reduction in microprocessors,” in Proceedings of IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD '05), pp. 253–257, San Jose, Calif, USA, October 2005.
View at: Publisher Site | Google Scholar
S. Borkar, P. Dubey, and K. Kahn et al., “Platform 2015: Intel Processor and Platform Evolution for the next Decade,” 2005, White Paper, Intel Corporation.
View at: Google Scholar
A. Edman and C. Svensson, “Timing closure through a globally synchronous, timing partitioned design methodology,” in Proceedings of the 41st Design Automation Conference (DAC '04), pp. 71–74, San Diego, Calif, USA, June 2004.
View at: Google Scholar
B. Black, D. W. Nelson, C. Webb, and N. Samra, “3D processing technology and its impact on IA32 microprocessors,” in Proceedings of IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD '04), pp. 316–318, San Jose, Calif, USA, October 2004.
View at: Publisher Site | Google Scholar
S. Das, A. Chandrakasan, and R. Reif, “Three-dimensional integrated circuits: performance, design methodology, and CAD tools,” in Proceedings of IEEE Computer Society Annual Symposium on VLSI (VLSI '03), pp. 13–18, Tampa, Fla, USA, February 2003.
View at: Google Scholar
W. J. Dally and J. W. Poulton, Digital Systems Engineering, Cambridge University Press, Cambridge, UK, 1998.
View at: Google Scholar
J. A. McNeill, “Jitter in ring oscillators,” IEEE Journal of Solid-State Circuits, vol. 32, no. 6, pp. 870–879, 1997.
View at: Publisher Site | Google Scholar
M. Mansuri and C.-K. K. Yang, “Jitter optimization based on phase-locked loop design parameters,” IEEE Journal of Solid-State Circuits, vol. 37, no. 11, pp. 1375–1382, 2002.
View at: Publisher Site | Google Scholar
H. B. Bakoglu and J. D. Meindl, “Optimal interconnection circuits for VLSI,” IEEE Transactions on Electron Devices, vol. 32, no. 5, pp. 903–909, 1985.
View at: Google Scholar
T. Sakurai, “Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSI's,” IEEE Transactions on Electron Devices, vol. 40, no. 1, pp. 118–124, 1993.
View at: Publisher Site | Google Scholar
M. Ghoneima and Y. Ismail, “Optimum positioning of interleaved repeaters in bidirectional buses,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 3, pp. 461–469, 2005.
View at: Publisher Site | Google Scholar
A. B. Kang, S. Muddu, E. Sarto, and R. Sharma, “Interconnect tuning strategies for high-performance ICs,” in Proceedings of the Design, Automation and Test in Europe (DATE '98), pp. 471–478, Paris, France, February 1998.
View at: Publisher Site | Google Scholar
K. Nose and T. Sakurai, “Two schemes to reduce interconnect delay in bi-directional and uni-directional buses,” in Proceedings of IEEE Symposium on VLSI Circuits (VLSIC '01), pp. 193–194, Kyoto, Japan, June 2001.
View at: Publisher Site | Google Scholar
K. Hirose and H. Yasuura, “A bus delay reduction technique considering crosstalk,” in Proceedings of the Design, Automation and Test in Europe Conference (DATE '00), pp. 441–445, Paris, France, March 2000.
View at: Publisher Site | Google Scholar
M. Pedram, Q. Wu, and X. Wu, “A new design of double edge triggered flip-flops,” in Proceedings of the 3rd Conference of the Asia and South Pacific Design Automation Conference (ASP-DAC '98), pp. 417–421, Yokohama, Japan, February 1998.
View at: Publisher Site | Google Scholar
R. Bashirullah, W. Liu, R. Cavin, and D. Edwards, “A hybrid current/voltage mode on-chip signaling scheme with adaptive bandwidth capability,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 8, pp. 876–880, 2004.
View at: Publisher Site | Google Scholar
Predictive Technology model, http://www.eas.asu.edu/~ptm/.

Copyright

Copyright © 2007 Maged Ghoneima et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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